1. Field of the Invention
This invention relates to a CMOS method of making a high voltage and a low voltage transistor simultaneously on the same chip.
2. Brief Description of the Prior Art
Increased emphasis is presently being placed upon the merger of high voltage (i.e., about 15 volts) and low voltage (i.e., about 5 volts) functions in 1 micron and submicron CMOS. This is particularly the case for application specific integrated circuit (ASIC) standard cell type applications wherein there is a desirability of merging high performance logic cells with analog and non-volatile EPROM and EEPROM circuits.
When operating at the 1 micron and submicron CMOS technology level, merging of low and high voltage functions becomes increasingly difficult to accomplish without excessive process complexity, i.e., a large increase in the number of lithography levels. The increase in process complexity results from the use of thinner gate oxides, typically 300 angstroms or less and short channel lengths, i.e., about 0.6 to 1.2 microns, which cause severe hot electron problems in the NMOS transistors at high drain voltages (&gt;about 5 volts). Hot electrons are high energy electrons generated in the channel region of a semiconductor device when the electric fields become excessively high. The hot electrons can then be ejected into the gate oxide and can cause reliability problems associated with the device thereby. An LDD is a well known technique to reduce the intensity of electric fields and, hence, the generation of hot electrons. As the gate length is shortened, a technique is required to reduce the hot electron generation, whereas, the higher the drain operating voltage, the greater will be the amount of hot electron generation. Therefore, it is necessary to have a different lightly doped drain structure for the high voltage transistor as compared with the low voltage device. If the same drain structure is used for both high and low voltage devices, the low voltage transistor performance is degraded, thereby requiring a trade-off as has been provided in the past.
Even long N-channel devices of about 3 microns can exhibit poor high voltage characteristics when fabricated with thin gate oxides. Similar problems are not encountered with the P-channel device because of the much lower coefficient of impact ionization for holes.
As a result of the NMOS hot electron/reliability issues, the high voltage transistor problem is usually solved by using a combination of thicker gate oxides and longer channel lengths for these devices. This usually means that two different gate oxide thicknesses have to be used in a "merged", i.e., high voltage-low voltage technology, one for low voltage/high peformance transistors and a thicker oxide for the high voltage devices. This adds significant process complexity and usually results in a two level polycrystalline silicon (polysilicon) process, the first being used for the gates of one type of transistor while the second level of polysilicon is used for the other type of transistor.
It is recognized that if it were possible for the low and high voltage transistors to share a common gate oxide thickness and therefore the same polysilicon gate electrode level, a significant reduction in process complexity could be realized. This type of structure has not been available in the prior art.